--- /dev/null
+diff -r d5eb5205ff35 tools/ioemu/hw/pci.c
+--- a/tools/ioemu/hw/pci.c Thu Aug 24 16:25:49 2006 +0100
++++ b/tools/ioemu/hw/pci.c Fri Aug 25 11:00:03 2006 +0800
+@@ -286,6 +286,7 @@ void pci_default_write_config(PCIDevice
+ case 0x0b:
+ case 0x0e:
+ case 0x10 ... 0x27: /* base */
++ case 0x2c ... 0x2f: /* subsystem vendor id, subsystem id */
+ case 0x30 ... 0x33: /* rom */
+ case 0x3d:
+ can_write = 0;
+@@ -318,6 +319,18 @@ void pci_default_write_config(PCIDevice
+ break;
+ }
+ if (can_write) {
++ if( addr == 0x05 ) {
++ /* In Command Register, bits 15:11 are reserved */
++ val &= 0x07;
++ } else if ( addr == 0x06 ) {
++ /* In Status Register, bits 6, 2:0 are reserved, */
++ /* and bits 7,5,4,3 are read only */
++ val = d->config[addr];
++ } else if ( addr == 0x07 ) {
++ /* In Status Register, bits 10,9 are reserved, */
++ val = (val & ~0x06) | (d->config[addr] & 0x06);
++ }
++
+ d->config[addr] = val;
+ }
+ addr++;
+diff -r d5eb5205ff35 tools/ioemu/hw/rtl8139.c
+--- a/tools/ioemu/hw/rtl8139.c Thu Aug 24 16:25:49 2006 +0100
++++ b/tools/ioemu/hw/rtl8139.c Fri Aug 25 11:00:03 2006 +0800
+@@ -3423,6 +3423,8 @@ void pci_rtl8139_init(PCIBus *bus, NICIn
+ pci_conf[0x0e] = 0x00; /* header_type */
+ pci_conf[0x3d] = 1; /* interrupt pin 0 */
+ pci_conf[0x34] = 0xdc;
++ pci_conf[0x2c] = pci_conf[0x00]; // same as Vendor ID
++ pci_conf[0x2d] = pci_conf[0x01];
+
+ s = &d->rtl8139;
+
+diff -r d5eb5205ff35 tools/ioemu/hw/usb-uhci.c
+--- a/tools/ioemu/hw/usb-uhci.c Thu Aug 24 16:25:49 2006 +0100
++++ b/tools/ioemu/hw/usb-uhci.c Fri Aug 25 11:00:03 2006 +0800
+@@ -659,6 +659,8 @@ void usb_uhci_init(PCIBus *bus, int devf
+ pci_conf[0x0e] = 0x00; // header_type
+ pci_conf[0x3d] = 4; // interrupt pin 3
+ pci_conf[0x60] = 0x10; // release number
++ pci_conf[0x2c] = pci_conf[0x00]; // same as Vendor ID
++ pci_conf[0x2d] = pci_conf[0x01];
+
+ for(i = 0; i < NB_PORTS; i++) {
+ qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach);